Toshiba Develops Worlds Fastest Device Controller for Embedded NAND Flash Memory Module Compliant with JEDEC UFS Ver..0 Standard

February 25, 2014

TOKYO Toshiba Corporation (TOKYO: 6502) today announced that it has developed the worlds fastest device controller for embedded NAND flash memory modules compliant with the Universal Flash Storage (UFS) Ver.2.0 and UFS Unified Memory Extension (UME) Ver.1.0 standards defined by JEDEC Solid State Technology Association (JEDEC). An embedded NAND flash memory module integrating the controller achieves a random read performance about 10 times faster than modules compliant with the e MMC [1] standard now widely used in low- to high-end mobile devices. The device controller secures a performance equivalent to that of Solid State Drives (SSDs) for personal computers in a package as small as a fingernail.

Toshiba presented the new device controller at the 2014 IEEE International Solid-State Circuits Conference (ISSCC) in San Francisco, California, on February 12.

Recent advances in CPU processing power and DRAM capacity in smartphones and tablet PCs allow users to enjoy more powerful applications, including high resolution video players and feature-rich games. Such devices also require embedded NAND flash memory modules as their main non-volatile storage. Going forward, the higher performance of embedded NAND Flash compliant with the UFS standard will secure its widespread use in high-end mobile devices.

Current embedded NAND flash memory modules are increasingly unable to store all the data required to execute commands received from the host in the on-chip RAM of their device controllers, largely because of its increasing size; the device controllers have to execute multiple reads of the command data from NAND flash memory, which slows command execution. The result is growing demand for improved random read performance and a better user experience. However, it is difficult to secure anything more than incremental improvement in random read performance, because it takes 10s of microseconds to read data from NAND flash memory.

Toshiba has developed a new device controller for embedded NAND flash memory module to overcome these issues.

The new device controller stores data for executing a command received from the host in the host-side DRAM, reducing the number of read operations from NAND flash memory. This halves the time required to process a read command. The procedure by which the device controller writes data to the host-side DRAM and reads data from host-side DRAM is compliant with the UFS UME Ver.1.0 standard, published at the same time as UFS Ver.2.0.

Toshiba has also developed a hardware engine that executes read commands received from the host in parallel and integrated it into the new device controller. It achieves more than two times higher random read performance compared with conventional technology.

These two new Toshiba technologies have realized embedded NAND flash memory modules with a device controller that attains over 60 kIOPS[2] in random read performance of 4 KB access[3]. This performance level is about 10 times higher than that of modules compliant with e MMC Version 5.0.

The new device controller also integrates new, Toshiba-designed, analog circuit technology that enables UFSs ultra-high-speed serial communication at 5.8Gbps per lane, which avoids any increase in power consumption.

Mobile devices with an embedded NAND flash memory module that uses the new device controller will offer higher random read performances that will improve response time in user interactions and shorter application start-up times, enhancing the overall user experience.

Sample shipping of embedded NAND flash memory modules with the new device controller are scheduled to start in the first half of CY2014.

Notes:

[1] e MMC is a trademark and a product category for a class of embedded memory products built to the JEDEC e MMC Standard specification.

[2] Input / Output Per Second, number of commands to complete in 1 second.

[3] Conditions are followings; number of NAND flash memory chips is 8, size of access region is 8 GB, and host latency is 1 microsecond.

LINK:	http://www.semicon.toshiba.co.jp/eng/profile/news/newsrelease/topics/t...
	See more stories from toshiba

Most recent headlines