Xilinx Debuts Industry-First P4_6 to FPGA Compilation and Introduces New P4-NetFPGA Workflow for Networking Researchers at P4 Industry Events

12/05/2017

Xilinx Debuts Industry-First P4_16 to FPGA Compilation and Introduces New P4-NetFPGA Workflow for Networking Researchers at P4 Industry Events May 11, 2017

SAN JOSE, Calif., May 11, 2017 /PRNewswire/ -- Xilinx, Inc. (NASDAQ: XLNX) announced today it will participate in the 2017 P4 Developer Day and P4 Workshop, May 16 - 17 at Stanford University, debuting its P416 to FPGA compilation and introducing a new P4-NetFPGA workflow for networking researchers. As co-chair of the P4.org working group that has developed the new P416 language standard, Xilinx is a lead sponsor and co-presenter for the two-day event. Join the 2017 P4 Developer Day and P4 Workshop to learn about the sessions and demonstrations and more. To register, visit http://p4.org/.

May 16 at Stanford University, Palo Alto, CA

P4-NetFPGA Workflow for Networking Researchers

At the 2017 P4 Developer Day, Xilinx will introduce the P4-NetFPGA workflow for networking researchers, developed in collaboration with Stanford University and the University of Cambridge. The new workflow couples the new Xilinx P416 to FPGA compilation capability with the Xilinx technology-powered open source NetFPGA SUME platform for networking research (netfpga.org). It allows researchers to easily conduct experiments in hardware operating at line rate. At the Developer Day, there will be a half-day hands-on laboratory allowing attendees to gain experience with P4-NetFPGA, including implementing In-band Network Telemetry.

May 17 at Stanford University, Palo Alto, CA

P416-to-FPGA Compilation Demonstration

At the 2017 P4 Workshop, where the new P416 language specification will be discussed, Xilinx will debut its P416 to FPGA compilation flow based on the Xilinx SDNet Development Environment for Networking. SDNet supports FPGA packet processing rates between 1 Gb/sec and 100 Gb/sec. At the workshop, an industry-first demonstration of joint work by Xilinx Labs and Stanford University will show stateful data plane processing for the TCP protocol implemented by compiling a P416 program to a Xilinx FPGA.

About Xilinx

Xilinx is the leading provider of All Programmable FPGAs, SoCs, MPSoCs, RFSoCs and 3D ICs. Xilinx uniquely enables applications that are both software defined and hardware optimized powering industry advancements in Cloud Computing, 5G Wireless, Embedded Vision, and Industrial IoT. For more information, visit www.xilinx.com.

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Copyright 2017 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners.

Xilinx

Amy Attard

(408) 879-6924

amya@xilinx.com

SOURCE Xilinx, Inc.

LINK:	https://www.xilinx.com/news/press/2017/xilinx-debuts-industry-first-p4...
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