SAN JOSE, Calif., Sept. 10, 2013 /PRNewswire/ -- Xilinx, Inc. (NASDAQ: XLNX) today announced the All Programmable Abstractions initiative to improve productivity of hardware designers and to empower systems and software developers to directly leverage All Programmable FPGA, SoCs, and 3D ICs. Xilinx and its ecosystem Alliance members including MathWorks and National Instruments now support a combination of software, model, platform, and IP-based design environments. These environments enable high-level graphical and text-based programming languages such as C, C , SystemC, and will soon support OpenCL (Open Computing Language) with advanced automation technology that translates these languages into optimized implementations. These software and system level abstractions complement hardware focused IP integration and C-based design abstractions that have already proven to accelerate development of complex FPGAs and SoCs up to 15X over traditional RTL flows.
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By expanding the number and type of abstractions designers can choose from, we are not only improving productivity for existing hardware customers, but are empowering the vast number of systems and software engineers to directly leverage All Programmable FPGAs, SoCs, and 3D ICs, said Tom Feist, sr. director, Design Methodology Marketing at Xilinx.
Accelerated Hardware Design
To accelerate the creation of highly integrated, complex designs in All Programmable devices, Xilinx has delivered Vivado IP Integrator (IPI). Vivado IPI accelerates the integration of customer IP, Xilinx LogiCORE and SmartCORE IP, third party IP, MathWorks Simulink designs built with Xilinxs System Generator, and C/C and System C synthesized IP with Vivado High-Level Synthesis (HLS).
Leveraging the combination of Vivado IPI and HLS has been invaluable to our development of next-generation cable infrastructure products which enable rapid deployment of new services through a software-driven, all-IP architecture, said Ties Bos, director of Software and FPGA at Gainspeed, Inc. The combination of these abstractions allowed us to develop our algorithms in C and rapidly integrate the resulting IP, saving greater than 15X in development costs versus an RTL approach.
Based on industry standards such as the ARM AXI interconnect and IP-XACT metadata for IP packaging, Vivado IPI delivers intelligent correct-by-construction assembly of designs co-optimized with Xilinx All Programmable solutions. When targeting a Zynq -7000 All Programmable SoC, embedded design teams can now more rapidly identify, reuse, and integrate both software and hardware IP targeted for the dual-core ARM processing system and high performance FPGA fabric.
Accelerated System-Level Design
Systems engineers prefer abstractions such as C/C /SystemC, OpenCL, MathWorks MATLAB and Simulink, and National Instruments LabVIEW to model the hardware and software behavior for todays smarter systems. Xilinx and its ecosystem of Alliance members enable design teams to take these algorithms directly to implementation without worrying about implementation details.
MathWorks has released a new guided workflow for Zynq-7000 All Programmable SoC devices with their R2013b release. The guided workflow enables software developers and hardware design engineers to create and model their algorithms in MATLAB and Simulink, partition their designs between software and hardware, and automatically target, integrate, debug and test those models on Xilinx targeted design platforms. Building on MathWorks extensive portfolio of application-specific toolbox libraries and robust embedded software and hardware code generation technology, this new functionality helps users verify and optimize system performance, and enables a wider community of developers to take advantage of the industrys first All Programmable SoC.
Embedded system designers use LabVIEW and NI reconfigurable I/O (RIO) hardware to abstract the complexity of traditional RTL design and avoid the time consuming tasks of building an operating system, drivers, and middleware for deployment targets. National Instruments created a platform-based approach to embedded design that includes off-the-shelf reconfigurable hardware and intuitive graphical programming. With a single-click, the NI LabVIEW 2013 development environment can compile, debug, and deploy applications written for processor or programmable logic on NI targets. This development environment currently supports multiple Xilinx All Programmable devices. NI chose Xilinx All Programmable SoCs and FPGAs for the RIO computing core, platform of over 60 deployable targets.
Working with several early customers, Xilinx is also developing a new, system-level, heterogeneous parallel programming environment that supports software-based programming, system verification, debug and automated implementation for C/C and OpenCL. This new comprehensive Eclipse -based environment will provide market-specific libraries to significantly improve design productivity. This new flow is architected to directly empower system architects, SW application developers, and embedded designers who require a parallel architecture, to increase system performance, reduce system BOM cost and deliver total power reduction with ease of use and development times in line with ASSPs, DSPs, and GPUs.
Accelerated Software Design
Xilinx All Programmable Abstractions also accelerate software development of the Zynq-7000 All Programmable SoC and MicroBlaze processor. Xilinx has developed a Quick Emulator (QEMU) open source virtual machine that emulates the system hardware/software interfaces. The earlier software development results in higher productivity, and continuous hardware/software integration validati
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SAN JOSE, Calif., Sept. 10, 2013 /PRNewswire/ -- Xilinx, Inc. (NASDAQ: XLNX) today announced the All Programmable Abstractions initiative to improve productivity of hardware designers and to empower systems and software developers to directly leverage All Programmable FPGA, SoCs, and 3D ICs. Xilinx and its ecosystem Alliance members including MathWorks and National Instruments now support a combination of software, model, platform, and IP-based design environments. These environments enable high-level graphical and text-based programming languages such as C, C , SystemC, and will soon support OpenCL (Open Computing Language) with advanced automation technology that translates these languages into optimized implementations. These software and system level abstractions complement hardware focused IP integration and C-based design abstractions that have already proven to accelerate development of complex FPGAs and SoCs up to 15X over traditional RTL flows. 
