SAN JOSE, Calif., Jan. 22, 2014 /PRNewswire/ -- Xilinx, Inc. (NASDAQ: XLNX) experts will highlight high-performance FPGA design techniques including 28Gbps backplane transceiver design, 3D stacked silicon package design, and comprehensive DDR4 signal-integrity analysis using high-performance UltraScale FPGA silicon and packaging at DesignCon 2014. Through a series of tutorials and paper presentations, Xilinx experts will share their insights for overcoming system-design challenges and increasing system performance. Learn more about Xilinx UltraScale multi-Gigabit transceivers, 3D stacked silicon, and advanced signal-integrity techniques at www.xilinx.com/products/technology/index.htm and by attending Xilinx presentations and tutorials at DesignCon 2014 January 28 - 31, 2014 at the Santa Clara Convention Center in Santa Clara, CA.(Logo: http://photos.prnewswire.com/prnh/20020822/XLNXLOGO)
Xilinx Tutorials
Tuesday, January 28, 2014 at 9:00 am - 12:00 pm, Ballroom K
Hands-On Tutorial for Fixture Removal of 28Gbps Tx Measurements
This tutorial will offer tips and advanced techniques for characterizing a 28Gbps transceiver. Leading experts will provide the opportunity for you to follow along with hands-on computer labs using the latest in software tools for measurement calibration and fixture characterization, simulated fixture channel verification and analysis, and synthesis with in-situ fixture de-embedding with measured data.
Tuesday, January 28, 2014 at 9:00 am - 12:00 pm, Ballroom E
High Density High Performance Package and 3D Interconnect Design
This tutorial is targeted at design and technology enablement for high-density and high-performance heterogeneous multi-chip integration with 3D interconnects. Multi-chip integration is defined by a broad range of high density interconnect technologies including high density PoP type package, SiP, SoP, TSV, and interposer, and most distinguishingly, addressing interconnect density at silicon level.
Tuesday, January 28, 2014 at 1:30 pm - 4:30 pm, Ballroom G
Relating COM to Familiar S-Parameter Parametric to Assist 25Gbps System Design
This tutorial will help bridge the gap between COM and traditional S-parameters. Attendees will explore correlating silicon level simulation with COM and how to link COM to passive link parameters such as IL, RL, ICR and ICN. Attendees will leave this session with straightforward system-design guidelines.
Xilinx Presentations
Wednesday, January 29, 2014 at 2:00 pm - 2:40 pm, Ballroom J
Touchstone v2.0 SI/PI S-Parameter Models for Simultaneous Switching Noise
This presentation will discuss how large-port-count v2.0 SI/PI Touchstone files with per-port reference impedances are invaluable in the design of DDR4 SDRAM interfaces and will show attendees how to analyze the simultaneous switching noise characteristics of single ended memory interfaces.
Wednesday, January 29, 2014 at 2:00 pm - 2:40 pm, Ballroom E
Distributed Modeling and Characterization of On-Chip/System Level PDN and Jitter Impact
This presentation will provide attendees with a methodology flow that enables characterization of a system-level power delivery network (PDN). The methodology takes into consideration the combined effects of chip, package, and board-level components of a PDN and results in very accurate prediction of power supply noise and its impact on system timing.
Thursday, January 30, 2014 at 9:20 am - 10:00 am, Ballroom C/D
Method for Analytically Calculating BER (Bit Error Rate) in Presence of Non-Linearity
This presentation offers a method for modifying the probability distribution function (PDF) to account for non-linearity. Once the PDF is correctly modified, the tail probability methods to determine BER as in a linear system analysis can be applied. This technique allows designers to combine any linear system with a non-linear system and use analytical methods to determine BER.
Thursday, January 30, 2014 at 10:15 am - 10:55 am, Ballroom F
Model Extraction and Circuit Simulation Approaches for Successful SSO Analysis of Chip-Package-Board Systems
This presentation will provide guidelines for extraction and transient circuit simulation to support SSO analysis for Chip-Package-Board systems; methods and options for extraction of the low frequency portion of broadband, high node-count S-parameter models for SSO analysis; and methods and options for transient circuit simulator application of high node-count S-parameter models for SSO analysis.
Thursday, January 30, 2014 at 11:05 am - 11:45 am, Ballroom C/D
High Speed Serial Link Simulation Based on Dynamic Modeling
This presentation will propose a new modeling architecture to resolve the problems faced with todays serial-link simulators, which can only perform static simulations based on the same set of interconnect s-parameter files and a given silicon PVT corner model. Todays approach does not reveal system performance in a changing environment. This new modeling architecture overcomes this limitation.
Thursday, January 30, 2014 at 2:50 pm - 3:30 pm, Ballroom E
Comprehensive Full-Chip Methodology to Verify Electromigration and Dynamic Voltage Drop on High Performance FPGA Designs in the 20nm Technology
This presentation will provide a comprehensive methodology to verify electromigration and dynamic voltage drop on high-performance 20nm FPGA designs. Various challenges to achieve proper coverage and predictable accuracy using EDA tool platforms will be discussed, along with challenges in deploying a scalable EM & IR solution for analog, full-custom, and SoC style designs.
Friday, January 31, 2014 at 10:40 am - 11:20 am, Ballroom H
De-Mystifying the 28 Gb/s SERDES Channel - Design to Measurement
This presentation will focus on designing 28Gbps channels that enable measurement verification of Tx performance; channel optimization and measurement techniques
