SAN JOSE, Calif., Dec. 10, 2013 /PRNewswire/ -- Xilinx, Inc. (NASDAQ: XLNX) today announced availability of its 20nm All Programmable UltraScale portfolio with product documentation and Vivado Design Suite support. Xilinx shipped its first 20nm silicon in early November 2013, continuing to execute on an aggressive UltraScale device rollout. These devices deliver an ASIC-class advantage with the industrys only ASIC-class programmable architecture coupled with the Vivado ASIC-strength design suite and UltraFast design methodology.
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(Photo: http://photos.prnewswire.com/prnh/20131210/SF30485-b)
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The new Xilinx UltraScale product portfolio extends Xilinxs market leading Kintex and Virtex FPGA and 3D IC families, based on the UltraScale architecture and the superior gate density of TSMCs 20SoC process. UltraScale devices enable 1.5x to 2x realizable system performance and integration, and consume up to half the power, relative to currently available solutions. These devices deliver next generation routing, ASIC-like clocking, and enhancements to logic and fabric to eliminate interconnect bottlenecks while supporting consistent device utilization of more than 90% without performance degradation.
Xilinx continues to lead in technology innovation and ground breaking product offerings that enable fastest time to market, said Moshe Gavrielov, president and CEO at Xilinx. UltraScale devices bring our customers ASIC-class capabilities by coupling our UltraScale ASIC-class architecture with our Vivado ASIC-strength design suite and UltraFast methodology. The combination of these silicon and design solutions enable the fastest path to achieve significant systems differentiation for our customers, and enables a far superior alternative to ASICs and ASSPs.
Our collaboration with Xilinx has resulted in the development and deployment of many new technologies and methodologies, said TSMC President and Co-CEO, Dr. Mark Liu. With the introduction of the first 20nm UltraScale Architecture products, Xilinx and TSMC demonstrate how the synergy between silicon process and device architecture extracts maximum product performance and results in the highest system value.
Kintex UltraScale Family
The new Kintex UltraScale FPGAs deliver up to 1.16M logic cells, 5,520 optimized DSP slices, 76 Mbits of BRAM, 16.3Gbps backplane-capable transceivers, PCIe Gen3 hard blocks, integrated 100Gb/s Ethernet MAC and 150Gb/s Interlaken IP Cores, and DDR4 memory interfaces. Initially introduced as part of the 28nm Xilinx 7 series family, Kintex devices established the new mid-range category of best price-performance at the lowest power. Kintex UltraScale devices are designed to continue leadership in this category to meet the requirements for the growing number of key applications including:
8K/4K Super High Vision Displays and Equipment
256-channel Ultrasound
8X8 Mixed Mode LTE and WCDMA radio with smart beamforming
100G Traffic Management/NIC
DOCSIS 3.1 CMTS equipment
Virtex UltraScale Family
Also setting new industry standards, the new Virtex UltraScale devices provide unprecedented levels of performance, system integration and bandwidth on a single chip. The largest family member delivers 4.4M logic cells, 1,456 user I/Os, 48 x 16.3 Gb/s backplane-capable transceivers and 89 Mbits of Block RAM, breaking previous records by more than doubling Xilinxs industrys highest capacity Virtex-7 2000T device and delivering a staggering 50M equivalent ASIC gates. Virtex UltraScale devices include 28Gb/s backplane-capable and 33Gb/s chip-to-optics transceivers, in addition to integrated PCIe Gen3, 100Gb/s Ethernet MAC and 150Gb/s Interlaken IP cores, and DDR4 memory interfaces to support multi-hundred gigabit-per-second levels of system performance with smart processing at full line rates.
The system performance and capacity delivered with the Virtex UltraScale family makes these devices the logical choice for the most challenging applications such as:
Single chip 400G MuxSAR
400G Transponder
400G MAC-to-Interlaken bridge
Emulation and Prototyping
Xilinx UltraScale devices provide the same performance of the logic fabric and key architectural blocks across the entire UltraScale portfolio, enabling a scalable and optimized architecture. Moreover, with footprint compatibility between families, Kintex UltraScale FPGAs provide a clear migration path to Virtex UltraScale devices. To learn what Xilinx Alliance Program members are saying about the new UltraScale products, read quotes below.
Availability
Xilinx UltraScale devices are sampling now. UltraScale devices are supported in the Vivado Design Suite 2013.4 release and full product documentation is now available at www.xilinx.com/kintex-ultrascale and www.xilinx.com/virtex-ultrascale. To learn more about the UltraScale architecture and to see a video of the industrys first 20nm silicon demonstrating 16.3Gbps over a backplane visit www.xilinx.com/ultrascale.
About Xilinx
Xilinx is the worlds leading provider of All Programmable FPGAs, SoCs, and 3D ICs. These industry-leading devices are coupled with a next-generation design environment and IP to serve a broad range of customer needs, from programmable logic to programmable systems integration. For more information, visit www.xilinx.com.
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Copyright 2013 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI, PCIe and PCI Express are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
Quote Sheet
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SAN JOSE, Calif., Dec. 10, 2013 /PRNewswire/ -- Xilinx, Inc. (NASDAQ: XLNX) today announced availability of its 20nm All Programmable UltraScale portfolio with product documentation and Vivado Design Suite support. Xilinx shipped its first 20nm silicon in early November 2013, continuing to execute on an aggressive UltraScale device rollout. These devices deliver an ASIC-class advantage with the industrys only ASIC-class programmable architecture coupled with the Vivado ASIC-strength design suite and UltraFast design methodology.
