DENVER, Colo.-SC13, Booth #4235, November 19, 2013 -Aspera, Inc., creators of next-generation software technologies that move the world's large data at maximum speed, have announced the results of a research project that Aspera Labs, the research arm of Aspera, has done in collaboration with Intel Corporation to investigate ultra high-speed (40 Gbps and beyond) data transfer solutions built on Intel Xeon processor E5-2600 product family-based systems and Aspera's fasp transport technology.
The initial research work between the two companies used the novel Intel Data Direct I/O Technology (Intel DDIO) and Single-Root I/O Virtualization (SR-IOV) resulting in 10 Gbps transfers, 300% improvement versus a baseline system, and similar results across both LAN and WAN environments, and across both physical and virtual environments.
Phase II of the research focused on an experimental integration between Aspera fasp and Intel Data Plane Development Kit (Intel DPDK), which makes it possible to directly access the network interface controller, bypassing the kernel networking stack. Using Intel DPDK, Aspera was able to boost single-stream data transfer speeds to 40 Gbps. Key benefits of the fasp prototype using Intel DPDK include:
Maximizing packet throughput by minimizing traditional CPU, memory, and I/O bottlenecks
Bypassing the kernel networking stack by reading data directly from storage into designated memory
Eliminating the per-packet processing bottleneck of using a socket-based interface
Reducing the number of memory copies needed to send and receive packets
Aspera's fasp transport technology was created to overcome the bottlenecks of traditional transport protocols in moving large data over the wide area network. Aspera fasp has no theoretical throughput limit, and is practically constrained by the available network bandwidth and the hardware resources at both ends of the transfers.
The Intel DPDK provides Intel architecture-optimized libraries that allow developers to focus on their application. Designed to accelerate packet processing performance, the Intel DPDK contains a growing number of libraries including memory and buffer management, queue/ring functions, flow classification, and NIC poll mode library. The Intel DPDK provides non-GPL source code libraries to support exceptional data plane performance and ease software development, while minimizing development time. It offers a simple software programming model that scales from Intel Atom to the latest Intel Xeon processors, providing flexible system configurations to meet any customer requirements for performance and scalable I/O.
The latest research results confirmed Aspera fasp can leverage modern computer, network and disk I/O architectures and development kits that enable efficient, low-latency, high-speed throughput.
Details about the tests including full results from the first phase research are published in a whitepaper developed by Aspera and Intel. Download here
Details about the latest tests using Intel DPDK are published in a whitepaper developed by Aspera and Intel. Download here
Demonstrations of Aspera ultra high-speed transfers will be available at SC13 at the Aspera Booth #4235.
Intel is a registered trademark of Intel Corporation in the United States and other countries.
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DENVER, Colo.-SC13, Booth #4235, November 19, 2013 -Aspera, Inc., creators of next-generation software technologies that move the world's large data at maximum speed, have announced the results of a research project that Aspera Labs, the research arm of Aspera, has done in collaboration with Intel Corporation to investigate ultra high-speed (40 Gbps and beyond) data transfer solutions built on Intel Xeon processor E5-2600 product family-based systems and Aspera's fasp transport technology. 
