While the performance breakthroughs associated with our new image sensor design mainly rest on its BSI architecture, there's more to the design. The new sensor also has several design features that boost performance beyond what BSI could accomplish alone particularly related to the ability to read out the massive amounts of imaging data at high speeds and improve throughput.
Solving Analog-to-Digital Conversion Challenges Embedding analog-to-digital converters (ADC) on CMOS image sensors is standard practice, but the BSI sensor's speed required a massive increase in the amount of ADC. While modern CMOS image sensors typically have between 1,000 and 10,000 embedded ADC, the new BSI high-speed sensor has 40,000 ADC, each converting every 523 ns and generating a large amount of data to off-load from the sensor. To accomplish this task, it incorporates 160 high-speed serial outputs operating at greater than 5 Gbps. This technology is common on CPUs and FPGAs but new on a high-speed imaging sensor.
The density of ADC on the new sensor did create power management and electrical crosstalk challenges, which were solved with the help of our design and integrated production partner, Forza Silicon. While simulations are often used in predicting sensor performance, this sensor required the simulation to calculate for weeks to provide a prediction. Forza has significant experience in simplifying simulations and analyzing actual versus predicted results for fast design modifications.
In the case of the BSI sensor, testing of early designs revealed a higher level of ADC crosstalk in both normal imaging and binning modes than our simulation tools had predicted, causing noticeable artifacts in the images. Forza engineers discovered that the crosstalk exhibited predictable patterns and developed modeling techniques that helped us eliminate the crosstalk altogether, which in turn mitigated imaging artifacts.
Binning for Maximum Throughput The sensor supports 2 x 2 binning to maximize throughput at faster speeds. Though not common in high-speed sensors, we've implemented binning in two previous cameras. It helps mitigate limitations of the sensor's column ADC architecture, enabling faster speeds than simply decreasing the y-dimension. This approach is subtly different from binning as applied in CCD cameras, where it's used to primarily boost sensitivity. In this case, we're using it to boost speed.
Although BSI is not a new technology, it's been used with great success in standard and cellphone cameras, by adapting it to high-speed imaging, we've been able to create a sensor that pushes the boundaries on speed in light-starved conditions.
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While the performance breakthroughs associated with our new image sensor design mainly rest on its BSI architecture, there's more to the design. The new sensor also has several design features that boost performance beyond what BSI could accomplish alone particularly related to the ability to read out the massive amounts of imaging data at high speeds and improve throughput. 
