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Xilinx, Arm, Cadence, and TSMC Announce Worlds First CCIX Silicon Demonstration Vehicle in 7nm Process Technology

13/09/2017

Xilinx, Arm, Cadence, and TSMC Announce Worlds First CCIX Silicon Demonstration Vehicle in 7nm Process Technology Sep 11, 2017

HSINCHU, Taiwan, Sept. 11, 2017 /PRNewswire/ -- Xilinx (NASDAQ: XLNX), Arm, Cadence Design Systems, Inc. (NASDAQ: CDNS) and TSMC (TWSE: 2330, NYSE: TSM) today announced a collaboration to build the first Cache Coherent Interconnect for Accelerators (CCIX) test chip in TSMC 7nm FinFET process technology for delivery in 2018. The test chip aims to provide a silicon proof point to demonstrate the capabilities of CCIX in enabling multi-core high-performance Arm CPUs working via a coherent fabric to off-chip FPGA accelerators.

About CCIX

Accelerating applications in the data center is a growing requirement due to power and space constraints. Applications such as big data analytics, search, machine learning, wireless 4G/5G, in-memory database processing, video analytics, and network processing benefit from acceleration engines that move data seamlessly among the various system components. CCIX will allow components to access and process data irrespective of where it resides, without the need for complex programming environments.

CCIX will leverage existing server interconnect infrastructure and deliver higher bandwidth, lower latency and cache coherent access to shared memory. This will result in a significant improvement in the usability of accelerators and overall performance and efficiency of data center platforms, lowering the barrier to entry into existing server systems and improving the total cost of ownership (TCO) of acceleration systems.

About the Test Chip

The test chip, implemented on TSMCs 7nm process, will be based on the latest Arm DynamIQ technology, CMN-600 coherent on-chip bus and foundation IP. To validate the complete subsystem, Cadence provided key I/O and memory subsystems, which include the CCIX IP solution (controller and PHY), PCI Express 4.0/3.0 (PCIe -4/3) IP solution (controller and PHY), the DDR4 PHY, peripheral IPs such as I2C, SPI and QSPI, as well as associated IP drivers. Cadence verification and implementation tools are being used to build the test chip. The test chip provides connectivity to Xilinxs 16nm Virtex UltraScale+ FPGAs over CCIX chip-to-chip coherent interconnect protocol.

Availability

The test chip will tape-out in early Q1 2018 with silicon availability expected in 2nd half 2018.

Company Quotes

Xilinx Quote

"As we work to innovate on advanced technology for compute acceleration, we are excited about the results of this collaboration," said Victor Peng, COO at Xilinx. "Our Virtex UltraScale+ HBM family is built using TSMCs 3rd generation CoWoS technology, which is now the industry standard assembly for HBM integration and cache-coherent acceleration with CCIX."

Arm Quote

"With the surge in artificial intelligence and big data, were seeing increasing demand for more heterogeneous compute across more applications," said Noel Hurley, vice president and general manager, Infrastructure Group, Arm. "The test chip will not only demonstrate how the latest Arm technology with coherent multichip accelerators can scale across the data center, but reinforces our commitment to solving the challenge of accessing data quickly and easily. This innovative and collaborative approach to coherent memory is a significant step forward in delivering high-performance, efficient data center platforms."

Cadence Quote

"By building an ecosystem for high-performance computing with our collaboration partners, we will enable our customers to quickly deploy innovative new architectures at 7nm and other advanced nodes for these growing data center applications," said Babu Mandava, senior vice president and general manager of the IP Group at Cadence. "The CCIX industry standard will help drive the next generation of interconnect that provides the high-performance cache coherency that the market is demanding."

TSMC Quote

"Artificial intelligence and deep learning will significantly impact industries including media, consumer electronics and healthcare," said Dr. Cliff Hou, TSMC vice president, Research & Development/Design and Technology Platform. "TSMCs most advanced 7nm FinFET process technology provides high performance and low power benefits that satisfy distinct product requirements for High-Performance Computing (HPC) applications targeting these markets."

About Xilinx

Xilinx is the leading provider of All Programmable semiconductor products, including FPGAs, SoCs, MPSoCs, RFSoCs, and 3D ICs. Xilinx uniquely enables applications that are both software defined and hardware optimized powering industry advancements in Cloud Computing, 5G Wireless, Embedded Vision, and Industrial IoT. For more information, visit www.xilinx.com.

About Arm

Arm technology is at the heart of a computing and connectivity revolution that is transforming the way people live and businesses operate. Our advanced, energy-efficient processor designs are enabling the intelligence in 100 billion silicon chips and securely powering products from the sensor to the smartphone to the supercomputer. With more than 1,000 technology partners including the worlds largest business and consumer brands, we are driving Arm innovation into all areas compute is happening inside the chip, the network and the cloud.

About Cadence

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence software, hardware and semiconductor IP are used by customers to deliver products to market faster. The companys System Design Enablement strategy helps customers develop differentiated products from chips to boards to systems in mobile, consumer, cloud datacenter, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Maga
LINK: https://www.xilinx.com/news/press/2017/xilinx-arm-cadence-and-tsmc-ann...
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